Buried Injector Logic, a Vertical Iil Using Deep Ion Implantation

A vertically integrated alternative for integrated injection logic has been realized, named buried injector logic (BIL). 1 MeV ion implantations are used to create buried layers. The vertical pnp and npn transistors have thin base regions and exhibit a limited charge accumulation if a gate is saturated. d.c. and dynamic analysis of BIL-gate behaviour are given. A minimum gate delay of well below 1 ns is projected if collector areas are smaller than 10 pm2 within an oxide isolated structure. A relation between maximum injector current density and device size is derived. NOTATION collector area effective gain (I,,,/Zb) of a gate upward current gain of the intrinsic npn transistor downward current gain of the extrinsic pnp transistor downward current gain of the intrinsic npn transistor upward current gain of the injector pnp transistor depletion layer capacitance (F/cm2) of the npn cb-junction depletion layer capacitance (F/cm2) of the ttpn eb-junction extrinsic base area around the first collector npn-emitter area extrinsic to the total base diffusion length extrinsic base area added for each next collector fanout, i.e. number of collectors per gate current injection parameter (nfqD/Q) maximum load current supplied to a gate maximmn collector current of npn transistor part of the total injector current that is not used for switching lateral current in the intrinsic npn-base lateral current in the npn-emitter injector current density electron current density across the pnp ebjunction collector length (y-direction) electron injection currents hole injection currents effective majority concentration (majority concentration corrected for bandgap narrowing and high injection) depletion layer charge active charge sheet resistance of the npn-emitter sheet resistance of the intrinsic npn-base downward intrinsic npn ce-transittime upward intrinsic npn ce-transittime downward extrinsic pnp ce-transittime gate delay time when no active charge is present minimum gate delay (active charges present) voltages normalized on kTlq logical “hiw voltage logical “low” voltage injector voltage Vllv, TPresent address: University of Zambia, School of Engineering, Lusaka, Zambia. V,(Y) potential in the instrinsic npn-base V,(Y) potential in the npn-emitter